Resistive random-access memory for exclusive nor (xnor) neural networks

ABSTRACT

A resistive random-access memory (RRAM) system includes an RRAM cell. The RRAM cell includes a first select line and a second select line, a word line, a bit line, a first resistive memory device, a first switching device, a second resistive memory device, a second switching device, and a comparator. The first resistive memory device is coupled between a first access node and the bit line. The first switching device is coupled between the first select line and the first access node. The second resistive memory device is coupled between a second access node and the bit line. The second switching device is coupled between the second select line and the second access node. The comparator includes a first input coupled to the bit line, a second input, and an output.

RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.16/921,198, filed Jul. 6, 2020, which is a continuation of U.S. PatentApplication No. 16/126,563, filed Sep. 10, 2018, issued as U.S. Pat. No.10,706,923, which claims the benefit of provisional patent applicationSer. No. 62/556,157, filed Sep. 8, 2017, the disclosures of which arehereby incorporated herein by reference in their entireties.

FIELD OF THE DISCLOSURE

The present disclosure relates to memory architectures for the efficientimplementation of deep neural networks.

BACKGROUND

Deep neural networks, and in particular convolutional neural networks,are being used with increasing frequency for a number of tasks such asimage classification, image clustering, and object recognition. In aforward propagation of a conventional convolutional neural network, akernel is passed over one or more tensors to produce one or more featuremaps. At a particular location of the kernel within a tensor, each of anumber of input values in the tensor operated on by the kernel aremultiplied by a corresponding weight value in the kernel and summed viaaddition and subtraction to produce a single value of a feature map.Accordingly, a conventional convolutional neural network requiresmultiplication, addition, and subtraction. Implementing a conventionalconvolutional neural network requires a large amount of computing power,and the technology has thus been unavailable for mobile and low-powerdevices such as those for the Internet of Things.

Recent work in the field has focused on reducing the necessary computingpower for implementing convolutional neural networks. A first approach,referred to as a “binary neural network,” uses binary weight values inthe kernel. By converting the weight values in the kernel to binaryvalues, a forward propagation of the binary neural network can becomputed using only addition and subtraction. Foregoing the need formultiplication during forward propagation may result in a 2× savings incomputing power. Further, storing binary weight values instead of realweight values may produce a 32× savings in memory. Finally, using binaryweight values results in minimal if any impact on the accuracy of thebinary neural network.

An additional approach, referred to as an “XNOR neural network,” usesbinary input values in the tensors and binary weight values in thekernel. By converting the input values in the tensors and the weightvalues in the kernel to binary values, a forward propagation of the XNORneural network can be computed using only an exclusive nor (XNOR)operation and a bit count operation, where a bit count operation issimply a count of the number of high bits in a given stream of binaryvalues. Using an XNOR operation and a bit count operation instead ofmultiplication, addition, and subtraction may result in a 58× savings incomputing power. Further, storing binary input values instead of realinput values and binary weight values instead of real weight values mayproduce a 32× savings in memory. While using binary input values andbinary weight values does reduce the accuracy of the XNOR neuralnetwork, the results are often still acceptable for use.

XNOR neural networks in particular have opened the possibility ofimplementation on mobile and other low-power devices. However,conventional computing systems are not well suited for the efficientimplementation of these XNOR neural networks. Accordingly, there is aneed for computing systems, and in particular memory architectures,capable of efficiently supporting the operation of XNOR neural networksfor improvements in speed and efficiency.

SUMMARY

In one embodiment, a resistive random-access memory (RRAM) systemincludes an RRAM cell. The RRAM cell includes a first select line and asecond select line, a word line, a bit line, a first resistive memorydevice, a first switching device, a second resistive memory device, asecond switching device, and a comparator. The first resistive memorydevice is coupled between a first access node and the bit line. Thefirst switching device is coupled between the first select line and thefirst access node. The second resistive memory device is coupled betweena second access node and the bit line. The second switching device iscoupled between the second select line and the second access node. Thecomparator includes a first input coupled to the bit line, a secondinput, and an output.

In one embodiment the RRAM system may further include memory controlcircuitry coupled to the RRAM cell, where the memory control circuitryis configured to set a resistance of the first resistive memory deviceto represent a binary weight value, set a resistance of the secondresistive memory device to represent a complement of the binary weightvalue, provide a signal representative of a binary input value to thefirst select line, provide a signal representative of a complement ofthe binary input value to the second select line, provide a referencesignal to the second input of the comparator, and provide an accesssignal at the word line. In response to the access signal, the firstswitching device couples the first select line to the first access nodeand the second switching device couples the second select line to thesecond access node. A resulting compare signal provided to the firstinput of the comparator through the first resistive memory device andthe second resistive memory device causes the comparator to provide anoutput signal at the output, which is representative of a binary valuethat is equal to an exclusive NOR of the binary weight value and thebinary input value.

Those skilled in the art will appreciate the scope of the presentdisclosure and realize additional aspects thereof after reading thefollowing detailed description of the preferred embodiments inassociation with the accompanying drawing figures.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

The accompanying drawing figures incorporated in and forming a part ofthis specification illustrate several aspects of the disclosure, andtogether with the description serve to explain the principles of thedisclosure.

FIG. 1 illustrates a resistive random-access memory (RRAM) systemaccording to one embodiment of the present disclosure.

FIG. 2 illustrates an RRAM cell according to one embodiment of thepresent disclosure.

FIG. 3 illustrates an RRAM cell according to on embodiment of thepresent disclosure.

DETAILED DESCRIPTION

The embodiments set forth below represent the necessary information toenable those skilled in the art to practice the embodiments andillustrate the best mode of practicing the embodiments. Upon reading thefollowing description in light of the accompanying drawing figures,those skilled in the art will understand the concepts of the disclosureand will recognize applications of these concepts not particularlyaddressed herein. It should be understood that these concepts andapplications fall within the scope of the disclosure and theaccompanying claims.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of the present disclosure. Asused herein, the term “and/or” includes any and all combinations of oneor more of the associated listed items.

It will be understood that when an element such as a layer, region, orsubstrate is referred to as being “on” or extending “onto” anotherelement, it can be directly on or extend directly onto the other elementor intervening elements may also be present. In contrast, when anelement is referred to as being “directly on” or extending “directlyonto” another element, there are no intervening elements present.Likewise, it will be understood that when an element such as a layer,region, or substrate is referred to as being “over” or extending “over”another element, it can be directly over or extend directly over theother element or intervening elements may also be present. In contrast,when an element is referred to as being “directly over” or extending“directly over” another element, there are no intervening elementspresent. It will also be understood that when an element is referred toas being “connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present.

Relative terms such as “below” or “above” or “upper” or “lower” or“horizontal” or “vertical” may be used herein to describe a relationshipof one element, layer, or region to another element, layer, or region asillustrated in the Figures. It will be understood that these terms andthose discussed above are intended to encompass different orientationsof the device in addition to the orientation depicted in the Figures.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the disclosure.As used herein, the singular forms “a,” “an,” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises,”“comprising,” “includes,” and/or “including” when used herein specifythe presence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this disclosure belongs. It willbe further understood that terms used herein should be interpreted ashaving a meaning that is consistent with their meaning in the context ofthis specification and the relevant art and will not be interpreted inan idealized or overly formal sense unless expressly so defined herein.

FIG. 1 shows a resistive random-access memory (RRAM) memory system 10according to one embodiment of the present disclosure. The RRAM system10 includes an array of RRAM units 12, comparator circuitry 14, andmemory control circuitry 16. The RRAM units 12 are each coupled betweenone of a number of word lines 18, one of a number of select lines 20,and one of a number of bit lines 22. The comparator circuitry 14 iscoupled between the bit lines 22 and the memory control circuitry 16.The memory control circuitry 16 is coupled to each one of the word lines18 and the select lines 20. While not shown, the memory controlcircuitry 16 may further be connected to each one of the bit lines 22 insome embodiments. In operation, the memory control circuitry 16 providessignals to each one of the word lines 18 and the select lines 20 inorder to read and write values to and from the RRAM units 12. Whenreading values from the RRAM units 12 an output indicative of the stateof the RRAM units 12 being read is generally provided on the bit line22.

Notably, while a select number of RRAM units 12 are shown forillustration, those skilled in the art will appreciate that the RRAMmemory system 10 may include any number of RRAM units 12 withoutdeparting from the principles of the present disclosure. Further, whilethe memory control circuitry 16 is shown as a single block in FIG. 1 ,those skilled in the art will appreciate that the memory controlcircuitry 16 may include multiple discrete parts, each of which isdesigned to perform a specific portion of the functionality describedherein.

In a conventional memory architecture, the comparator circuitry 14 iseliminated and each one of the RRAM units 12 is operated as a memorycell suitable for storing and retrieving a single bit. Such a memoryarchitecture is inefficient, for example, when used for the storage ofdata associated with an XNOR neural network. In the conventional memoryarchitecture, each one of the input values and weight values must beseparately stored in a different RRAM unit 12. Further, the RRAM units12 must be individually addressed to retrieve the stored contentsthereof. Accordingly, only a subset of the RRAM units 12 can be read ata time, which often results in a large number of read operations foreach forward propagation of an XNOR neural network. Further, the XNORoperation and the bit count operation must be performed by processingcircuitry external to the RRAM system 10, which requires additional readand write operations as the data is provided to and from this externalprocessing circuitry. Due to all of the factors discussed above,conventional memory architectures result in a large amount ofinefficiency when used with an XNOR neural network.

Accordingly, FIG. 2 shows an RRAM cell 24 according to one embodiment ofthe present disclosure. The memory control circuitry 16 is shown forcontext. The RRAM cell 24 includes a first RRAM unit 12A, a second RRAMunit 12B, and a comparator 26 coupled between a word line 18, a firstselect line 20A, a second select line 20B, and a bit line 22. The firstRRAM unit 12A includes a first switching device 28A coupled in serieswith a first resistive memory device 30A between the first select line20A and the bit line 22. The first switching device 28A is shown as atransistor including a control input coupled to the word line 18, afirst switching input coupled to the first select line 20A, and a secondswitching input coupled to a first access node 32A, which is in turncoupled to the first resistive memory device 30A. The second RRAM unit12B includes a second switching device 28B coupled in series with asecond resistive memory device 30B between the second select line 20Band the bit line 22. The second switching device 28B is shown as atransistor including a control input coupled to the word line 18, afirst switching input coupled to the second select line 20B, and asecond switching input coupled to a second access node 32B, which is inturn coupled to the second resistive memory device 30B. The comparator26 forms a portion of the comparator circuitry 14 and includes a firstinput 34A coupled to the bit line 22, a second input 34B coupled to thememory control circuitry 16, and an output 34C coupled to the memorycontrol circuitry

The RRAM cell 24 is configured to perform an XNOR operation between abinary input value and a binary weight value. The result of the XNORoperation across multiple RRAM cells 24 may be aggregated with a bitcount operation such that a plurality of RRAM cells 24 can besimultaneously read. In operation, the memory control circuitry 16performs a write operation by setting a resistance of the firstresistive memory device 30A to represent a binary weight value (theresistance representing the binary weight value is illustrated as W). Inone embodiment, a binary high state (e.g., “1”) is represented as a lowresistance and a binary low state (e.g., “0,” or “−1” in the case ofXNOR neural networks wherein binary values are represented as either “1”or “−1”) is represented as a high resistance. The memory controlcircuitry 16 further sets a resistance of the second resistive memorydevice 30B to represent a complement of the binary weight value (theresistance representing the complement of the binary weight value isillustrated as W). For example, if the binary weight value is a binaryhigh state, the resistance of the first resistive memory device 30A willbe set to a low resistance while the resistance of the second resistivememory device 30B will be set to a high resistance, and vice versa.Those skilled in the art will appreciate that resistive memory devicesare capable of storing values by changing a resistance thereof between ahigh resistance value and a low resistance value, and that theparticular magnitude of the high resistance and the low resistance asreferred to herein depends on the particular design of the resistivememory device. As discussed herein, the high resistance is a resistancethat is measurably higher than the low resistance, and in someembodiments the high resistance is at least an order of magnitude largerthan the low resistance. For purposes of discussion, it can be assumedthat the low resistance state is 0Ω and the high resistance state is ∞Ω.

The memory control circuitry 16 performs a read operation by providing asignal representative of a binary input value (the signal representativeof the binary input value is illustrated as IN) to the first select line20A and providing a signal representative of a complement of the binaryinput value (the signal representative of the complement of the binaryinput value is illustrated as IN) to the second select line 20B. Forpurposes of discussion herein, a binary high state may be represented bya positive voltage (e.g., 2V) while a binary low state may berepresented by a zero voltage. Those skilled in the art will appreciatethat the particular voltage and/or current levels for representingbinary values may be changed without departing from the principles ofthe present disclosure. The memory control circuitry 16 further providesa reference signal REF to the second input of the comparator 26.Finally, the memory control circuitry 16 provides an access signal ACCat the word line 18. As discussed herein, the access signal ACC is asignal that causes the first switching device 28A to couple (i.e.,provide a low resistance path) the first select line 20A to the firstaccess node 32A and the second switching device 28B to couple the secondselect line 20B to the second access node 32B. When an access signal ACCis not provided the word line 18 is generally kept at a zero voltage (ora voltage below a threshold voltage of the switching devices 28),causing the first switching device 28A to decouple (i.e., provide a highresistance path) the first select line 20A from the first access node32A and the second switching device 28B to decouple the second selectline 20B from the second access node 32B.

When the memory control circuitry 16 performs the read operation asdiscussed above, a current is produced through the first resistivememory device 30A and the second resistive memory device 30B andcombined to form a compare signal CMP at the bit line 22. The currentthrough the first resistive memory device 30A is determined by thevoltage of the signal representative of the binary input value INprovided at the first select line 20A and the resistance representativeof the binary weight value W at which the first resistive memory device30A is set. The current through the second resistive memory device 30Bis determined by the voltage of the signal representative of thecomplement of the binary input value IN provided at the second selectline 20B and the resistance representative of the complement of thebinary weight value W at which the second resistive memory device 30B isset. The combined current through the first resistive memory device 30Aand the second resistive memory device 30B is provided as a comparesignal CMP to the first input 34A of the comparator 26. The comparator26 compares the compare signal CMP to the reference signal REF toprovide an output signal OUT such that the output signal OUT isrepresentative of a binary value that is equal to an exclusive NOR ofthe binary weight value and the binary input value.

As an example, when the binary input value and the binary weight valueare both binary high states, the first resistive memory device 30A has alow resistance and the second resistive memory device 30B has a highresistance. Further, the signal representative of the binary input valueIN at the first select line 20A is a positive voltage while the signalrepresentative of the complement of the binary input value IN at thesecond select line 20B is a zero voltage. Accordingly, a large currentis produced through the first resistive memory device 30A and a zero ornegligible current is produced through the second resistive memorydevice 30B. The resulting compare signal CMP is a large currentapproximately equal to the current through the first resistive memorydevice 30A. The reference signal REF is set such that in response to thelarge current as the compare signal CMP, the comparator 26 provides theoutput signal OUT as a signal representative of a binary high state.Those skilled in the art will readily understand that the particularmagnitude of the large current and the small current are dependent onthe resistance of the resistive memory elements 30 as well as the levelof the signals used to represent a binary high state in the memorysystem. In general, the large current is measurably larger than thesmall current, and in some embodiments the large current is at least anorder of magnitude larger than the small current.

As an additional example, when the binary input value is a binary highstate and the binary weight value is a binary low state, the firstresistive memory device 30A has a high resistance and the secondresistive memory device 30B has a low resistance. Further, the signalrepresentative of the binary input value IN at the first select line 20Ais a positive voltage while the signal representative of the complementof the binary input value IN at the second select line 20B is a zerovoltage. Accordingly, a small current is produced through the firstresistive memory device 30A and a zero or negligible current is producedthrough the second resistive memory device 30B. The resulting comparesignal CMP is a small current approximately equal to the current throughthe first resistive memory device 30A. The reference signal REF is setsuch that in response to the small current as the compare signal CMP,the comparator 26 provides the output signal as a signal representativeof a binary low state.

Those skilled in the art will readily appreciate that when the binaryinput value is a binary low state and the binary weight value is abinary high state, the output signal OUT will be representative of abinary low state, and when the binary input value is a binary low stateand the binary weight value is a binary low state, the output signal OUTwill be representative of a binary high state. Accordingly, the RRAMcell 24 is configured to perform an XNOR operation between the binaryinput value and the binary weight value.

As discussed above, an RRAM cell 24 may be arranged in an array with oneor more other RRAM cells 24, wherein each RRAM cell 24 includes twoadjacent RRAM units 12 as illustrated in FIG. 1 and a comparator 26. Theoutput signal OUT from every comparator 26 in a row of RRAM cells 24 maybe summed to provide an aggregated output signal, which isrepresentative of a bit count of the exclusive NOR operations performedat each RRAM cell 24 in the row. Analog-to-digital converter (ADC)circuitry (not shown) may digitize the aggregated output signal togenerate a digital number that is the bit count of the exclusive NORoperations for a given number of RRAM cells 24. Since the bit countoperation does not require knowledge of the location of the high bits,it can be performed without individual addressing of the RRAM units 12,which allows for the simultaneous readout of an arbitrary number of RRAMcells 24.

In some embodiments, one comparator 26 may be shared between multipleRRAM cells 24. For example, each row of RRAM cells 24 as shown in FIG. 1may share a single comparator 26. In such an embodiment, the comparesignal CMP provided to the first input 34A of the comparator 26 is anaggregated compare signal CMP from multiple RRAM cells 24. The referencesignal REF is set in order to determine the number of high and lowcurrents that are summed at the bit line 22 in such an embodiment, suchthat the output signal OUT of the comparator 26 is a bit count of theexclusive NOR operations performed by the RRAM cells 24.

In some situations, it may be undesirable for the memory controlcircuitry 16 to generate the reference signal REF, as this maycomplicate the memory control circuitry 16. Accordingly, FIG. 3 shows anRRAM cell 36 according to an additional embodiment of the presentdisclosure. The RRAM cell 36 includes a first RRAM unit 12A, a secondRRAM unit 12B, a third RRAM unit 12C, a fourth RRAM unit 12D, and acomparator 38 coupled between a word line 18, a first select line 20A, asecond select line 20B, a first bit line 22A, and a second bit line 22B.The memory control circuitry 16 is shown for context. The first RRAMunit 12A includes a first switching device 40A coupled in series with afirst resistive memory device 42A between the first select line 20A andthe first bit line 22A. The first switching device 40A is shown as atransistor including a control input coupled to the word line 18, afirst switching input coupled to the first select line 20A, and a secondswitching input coupled to a first access node 44A, which is in turncoupled to the first resistive memory device 42A. The second RRAM unit12B includes a second switching device 40B coupled in series with asecond resistive memory device 42B between the second select line 20Band the first bit line 22A. The second switching device 40B is shown asa transistor including a control input coupled to the word line 18, afirst switching input coupled to the second select line 20B, and asecond switching input coupled to a second access node 44B, which is inturn coupled to the second resistive memory device 42B. The third RRAMunit 12C includes a third switching device 40C coupled in series with athird resistive memory device 42C between the first select line 20A andthe second bit line 22B. The third switching device 40C is shown as atransistor including a control input coupled to the word line 18, afirst switching input coupled to the first select line 20A, and a secondswitching input coupled to a third access node 44C, which is in turncoupled to the third resistive memory device 42C. The fourth RRAM unit12D includes a fourth switching device 40D coupled in series with afourth resistive memory device 42D between the second select line 20Band the second bit line 22B. The fourth switching device 40D is shown asa transistor including a control input coupled to the word line 18, afirst switching input coupled to the second select line 20B, and asecond switching input coupled to a fourth access node 44D, which is inturn coupled to the fourth resistive memory device 42D. The comparator38 forms a portion of the comparator circuitry 14 and includes a firstinput 46A coupled to the first bit line 22A, a second input 46B coupledto the second bit line 22B, and an output 46C coupled to the memorycontrol circuitry 16.

The RRAM cell 36 is configured to perform an XNOR operation between abinary input value and a binary weight value. The result of the XNORoperation across multiple RRAM cells 36 may be aggregated with a bitcount operation such that a plurality of RRAM cells 36 can besimultaneously read. In operation, the memory control circuitry 16performs a write operation by setting a resistance of the firstresistive memory device 42A and the fourth resistive memory device 42Dto represent a binary weight value (the resistance representing thebinary weight value is illustrated as W). As discussed above, in oneembodiment, a binary high state (e.g., “1”) is represented as a lowresistance and a binary low state (e.g., “0,” or “−1”) is represented asa high resistance. The memory control circuitry 16 further sets aresistance of the second resistive memory device 42B and the thirdresistive memory device 42C to represent a complement of the binaryweight value (the resistance representing the complement of the binaryweight value is illustrated as W). For example, if the binary weightvalue is a binary high state, the resistance of the first resistivememory device 42A and the fourth resistive memory device 42D will be setto a low resistance while the resistance of the second resistive memorydevice 42B and the third resistive memory device 42C will be set to ahigh resistance. Those skilled in the art will appreciate that resistivememory devices are capable of storing values by changing a resistancethereof between a high resistance value and a low resistance value, andthat the particular magnitude of the high resistance and the lowresistance as referred to herein depends on the particular design of theresistive memory device. As discussed herein, the high resistance is aresistance that is measurably higher than the low resistance, and insome embodiments the high resistance is at least an order of magnitudelarger than the low resistance. For purposes of discussion, it can beassumed that the low resistance state is 0Ω and the high resistancestate is ∞Ω.

The memory control circuitry 16 performs a read operation by providing asignal representative of a binary input value (the signal representativeof the binary input value is illustrated as IN) to the first select line20A and providing a signal representative of a complement of the binaryinput value (the signal representative of the complement of the binaryinput value is illustrated as IN) to the second select line 20B. Forpurposes of discussion herein, a binary high state may be represented bya positive voltage (e.g., 2V) while a binary low state may berepresented by a zero voltage. Those skilled in the art will appreciatethat the particular voltage and or current levels for representingbinary values may be changed without departing from the principles ofthe present disclosure. The memory control circuitry further provides anaccess signal ACC at the word line 18. As discussed herein, the accesssignal ACC is a signal that causes the first switching device 40A tocouple (i.e., provide a low resistance path) the first select line 20Ato the first access node 44A, the second switching device 40B to couplethe second select line 20B to the second access node 44B, the thirdswitching device 40C to couple the first select line 20A to the thirdaccess node 44C, and the fourth switching device 40D to couple thesecond select line 20B to the fourth access node 44D. When an accesssignal ACC is not provided the word line 18 is generally kept at a zerovoltage (or a voltage below a threshold voltage of the switching devices40), causing the first switching device 40A to decouple (i.e., provide ahigh resistance path) the first select line 20A from the first accessnode 44A, the second switching device 40B to decouple the second selectline 20B from the second access node 44B, the third switching device 40Cto decouple the first select line 20A from the third access node 44C,and the fourth switching device 40D to decouple the second select line20B from the fourth access node 44D.

When the memory control circuitry 16 performs the read operation asdiscussed above, a current is produced through the first resistivememory device 42A and the second resistive memory device 42B at thefirst bit line 22A and a current is produced through the third resistivememory device 42C and the fourth resistive memory device 42D at thesecond bit line 22B. The current through the first resistive memorydevice 42A is determined by the voltage of the signal representative ofthe binary input value IN provided at the first select line 20A and theresistance representative of the binary weight value W at which thefirst resistive memory device 42A is set. The current through the secondresistive memory device 42B is determined by the voltage of the signalrepresentative of the complement of the binary input value IN providedat the second select line 20B and the resistance representative of thecomplement of the binary weight value W at which the second resistivememory device 42B is set. The current through the third resistive memorydevice 42C is determined by the voltage of the signal representative ofthe binary input value IN provided at the first select line 20A and theresistance representative of the complement of the binary weight value Wat which the third resistive memory device 42C is set. The currentthrough the fourth resistive memory device 42D is determined by thevoltage of the signal representative of the complement of the binaryinput value IN provided at the second select line 20B and the resistancerepresentative of the binary weight value W at which the fourthresistive memory device 42D is set. The combined current through thefirst resistive memory device 42A and the second resistive memory device42B is provided as a first compare signal CMP₁ to the first input 46A ofthe comparator 38. The combined current of the third resistive memorydevice 42C and the fourth resistive memory device 42D is provided as asecond compare signal CMP₂ to the second input 46B of the comparator 38.The comparator 38 compares the first compare signal CMP₁ to the secondcompare signal CMP₂ to provide an output signal OUT, wherein the outputsignal is representative of a binary high state when the first comparesignal CMP₁ is greater than the second compare signal CMP₂ and theoutput signal OUT is representative of a binary low state when thesecond compare signal CMP₂ is greater than the first compare signalCMP₁. Accordingly, a binary value of the output signal OUT is equal toan exclusive NOR of the binary weight value and the binary input value.

As an example, when the binary input value and the binary weight valueare both binary high states, the first resistive memory device 42A andthe fourth resistive memory device 42D have a low resistance while thesecond resistive memory device 42B and the third resistive memory device42C have a high resistance. Further, the signal representative of thebinary input value IN at the first select line 20A is a positive voltagewhile the signal representative of the complement of the binary inputvalue IN at the second select line 20B is a zero voltage. Accordingly, alarge current is produced through the first resistive memory device 42A,a zero or negligible current is produced through the second resistivememory device 42B, a small current is produced through the thirdresistive memory device 42C, and a zero or negligible current isproduced through the fourth resistive memory device 42D. The resultingfirst compare signal CMP₁ is a large current approximately equal to thecurrent through the first resistive memory device 42A, and the resultingsecond compare signal CMP₂ is a small current approximately equal to thecurrent through the third resistive memory device 42C. Since the firstcompare signal CMP₁ is significantly larger than the second comparesignal CMP₂, the comparator 38 provides the output signal OUT as asignal representative of a binary high state. Those skilled in the artwill readily understand that the particular magnitude of the largecurrent and the small current are dependent on the resistance of theresistive memory elements 30 as well as the level of the signals used torepresent a binary high state in the memory system. In general, thelarge current is measurably larger than the small current, and in someembodiments the large current is at least an order of magnitude largerthan the small current.

As an additional example, when the binary input value is a binary highstate and the binary weight value is a binary low state, the firstresistive memory device 42A and the fourth resistive memory device 42Dhave a high resistance while the second resistive memory device 42B andthe third resistive memory device 42C have a low resistance. Further,the signal representative of the binary input value IN at the firstselect line 20A is a positive voltage while the signal representative ofthe complement of the binary input value IN at the second select line20B is a zero voltage. Accordingly, a small current is produced throughthe first resistive memory device 42A, a zero or negligible current isproduced through the second resistive memory device 42B, a large currentis produced through the third resistive memory device 42C, and a zero ornegligible current is produced through the fourth resistive memorydevice 42D. The resulting first compare signal CMP₁ is a small currentapproximately equal to the current through the first resistive memorydevice 42A, and the resulting second compare signal CMP₂ is a largecurrent approximately equal to the current through the third resistivememory device 42C. Since the second compare signal CMP₂ is significantlylarger than the first compare signal CMP₁, the comparator 38 providesthe output signal OUT as a signal representative of a binary low state.

Those skilled in the art will readily appreciate that when the binaryinput value is a binary low state and the binary weight value is abinary high state, the output signal OUT will be representative of abinary low state, and when the binary input value is a binary low stateand the binary weight value is a binary low state, the output signal OUTwill be representative of a binary high state. Accordingly, the RRAMcell 36 is configured to perform an XNOR operation between the binaryinput value and the binary weight value.

As discussed above, an RRAM cell 36 may be arranged in an array with oneor more other RRAM cells 36, wherein each RRAM cell 36 includes fouradjacent RRAM units 12 as illustrated in FIG. 1 and a comparator 38. Theoutput signal OUT from every comparator 38 in a row of RRAM cells 36 maybe summed to provide an aggregated output signal, which isrepresentative of a bit count of the exclusive NOR operations performedat each RRAM cell 36. ADC circuitry (not shown) may digitize theaggregated output signal to generate a digital number that is the bitcount of the exclusive NOR operations for a given number of RRAM cells36. Since the bit count operation does not require knowledge of thelocation of the high bits, it can be performed without individualaddressing of the RRAM units 12, which allows for the simultaneousreadout of an arbitrary number of RRAM cells 36.

Those skilled in the art will recognize improvements and modificationsto the preferred embodiments of the present disclosure. All suchimprovements and modifications are considered within the scope of theconcepts disclosed herein and the claims that follow.

What is claimed is:
 1. A resistive random-access memory (RRAM) systemcomprising: an RRAM cell comprising: a first select line and a secondselect line; a word line; a bit line; a first resistive memory devicecoupled between a first access node and the bit line; a first switchingdevice coupled between the first select line and the first access node;a second resistive memory device coupled between a second access nodeand the bit line; a second switching device coupled between the secondselect line and the second access node; and a comparator comprising afirst input coupled to the bit line, a second input, and an output.